/*
 * Academic License - for use in teaching, academic research, and meeting
 * course requirements at degree granting institutions only.  Not for
 * government, commercial, or other organizational use.
 *
 * File: IF_Control.c
 *
 * Code generated for Simulink model 'IF_Control'.
 *
 * Model version                  : 1.49
 * Simulink Coder version         : 9.8 (R2022b) 13-May-2022
 * C/C++ source code generated on : Tue Sep 10 22:33:31 2024
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: ARM Compatible->ARM Cortex-M
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#include "IF_Control.h"
#include "rtwtypes.h"
#include "Current_Loop.h"
#include "rt_nonfinite.h"

/* Block signals (default storage) */
B_IF_Control_T IF_Control_B;

/* Block states (default storage) */
DW_IF_Control_T IF_Control_DW;

/* External inputs (root inport signals with default storage) */
ExtU_IF_Control_T IF_Control_U;

/* Real-time model */
static RT_MODEL_IF_Control_T IF_Control_M_;
RT_MODEL_IF_Control_T *const IF_Control_M = &IF_Control_M_;

/* Model step function */
void IF_Control_step(real32_T arg_Iq_Set, real32_T arg_Target_Speed, real32_T
                     arg_Iabc[3], real32_T arg_Vabc_PU[3], real32_T *arg_Out1)
{
  /* Copy value for root inport '<Root>/Iq_Set' since it is accessed globally */
  IF_Control_U.iq = arg_Iq_Set;

  /* Copy value for root inport '<Root>/Target_Speed' since it is accessed globally */
  IF_Control_U.speed = arg_Target_Speed;

  /* Copy value for root inport '<Root>/Iabc' since it is accessed globally */
  {
    int32_T i;
    for (i = 0; i < 3; i++) {
      IF_Control_U.iabc[i] = arg_Iabc[i];
    }
  }

  /* Outputs for Atomic SubSystem: '<Root>/Current_Loop' */
  IF_Control_Current_Loop();

  /* End of Outputs for SubSystem: '<Root>/Current_Loop' */

  /* Outport: '<Root>/Vabc_PU' */
  arg_Vabc_PU[0] = IF_Control_B.Add[0];
  arg_Vabc_PU[1] = IF_Control_B.Add[1];
  arg_Vabc_PU[2] = IF_Control_B.Add[2];

  /* Outport: '<Root>/Theta_E' */
  *arg_Out1 = IF_Control_B.Merge1;
}

/* Model initialize function */
void IF_Control_initialize(void)
{
  /* Registration code */

  /* initialize non-finites */
  rt_InitInfAndNaN(sizeof(real_T));
}

/* Model terminate function */
void IF_Control_terminate(void)
{
  /* (no terminate code required) */
}

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
